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Subversion Repositories ion

[/] - Rev 85

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Rev	Log message	Author	Age	Path
85	BUG FIX: log2 function was wrong	ja_rd	4880d 15h	/
84	Added 'trigger address' for file logging to both the vhdl TB and the python script	ja_rd	4880d 15h	/
83	BUG FIX: LHU was not doing sign extension properly BUG FIX: SLTIU decoding was wrong	ja_rd	4880d 15h	/
82	bug fix: SLTI wasn't working properly in some cases	ja_rd	4882d 16h	/
81	Added a wait state to the SRAM area for the DE-1 demo code	ja_rd	4889d 10h	/
80	Stub cache fixed Now supports code refills from static 16- and 8- bit memory Plus many mirror corrections	ja_rd	4889d 10h	/
79	modelsim wave window script updated	ja_rd	4890d 12h	/
78	Code sample 'memtest' adapted to test read from flash	ja_rd	4890d 13h	/
77	Simulation template now supports simulated flash Synthesis template adapted to latest cache interface Python script now supports simulated flash	ja_rd	4890d 13h	/
76	Adapted pregenerated vhdl files to latest changes	ja_rd	4890d 13h	/
75	Added support for 8-bit-wide static memory (e.g. Flash) Updated demo 'top' file to use the DE-1 onboard flash	ja_rd	4890d 13h	/
74	Fixed (harmless) error in simulation template 2	ja_rd	4890d 17h	/
73	Fixed comment about write cycles in cache module	ja_rd	4890d 17h	/
72	Fixed stupid bug in SRAM write cycles (setup time violated) Wait states implemented for SRAM wait and read cycles	ja_rd	4890d 17h	/
71	Doc updated to reflect last changes	ja_rd	4891d 05h	/
70	updated CodeBlocks project file	ja_rd	4891d 05h	/
69	Updated simulation scripts Obsolete sim script removed	ja_rd	4891d 05h	/
68	Updated pre-generated vhdl files	ja_rd	4891d 05h	/
67	Deprecated files: Marked three files as unused, to be removed	ja_rd	4891d 05h	/
66	Code samples: Updated all code samples to use TB2 template and new memory map	ja_rd	4891d 05h	/

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Subversion Repositories ion

[/] - Rev 85

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