URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] - Rev 18

Rev	Log message	Author	Age	Path
18	A bunch of synthesis error/warning removed. Master and analyzer synthesis OK on Spartan6 FPGA	acapola	5011d 15h	/
17	yet another fix of the analyzer: ATR, and convention handling	acapola	5028d 14h	/
16	just cosmetic	acapola	5032d 14h	/
15	tpdu level tasks inverse convention	acapola	5033d 13h	/
14	Task to send strings as bytes improved	acapola	5036d 12h	/
13	Corrections in analyzer to handle TDi and historical bytes in ATR and PPS todo: handle inverse convention	acapola	5037d 16h	/
12	pps sequence added to test bench endOfTx added to TxCore	acapola	5048d 12h	/
11	added BSD licence header to files	acapola	5048d 16h	/
10	communication direction probe added	acapola	5048d 17h	/
9	parity convention fixed	acapola	5054d 14h	/
8		acapola	5056d 12h	/
7	- rx/tx use "cyclesPerEtu" input - "stopBit" status bit timing fixed - analyzer: "lastByte" and "bytesCnt" functional	acapola	5057d 12h	/
6	analyzer added to test bench, not functional yet...	acapola	5058d 12h	/
5	draft of t=0 protocol analyzer (to ease debuging, and eventually as an ip itself)	acapola	5059d 12h	/
4	Basic test bench completed for T=0: a card send ATR, reader send a command TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)	acapola	5060d 13h	/
3	initial draft, not functional yet	acapola	5067d 14h	/
2		acapola	5067d 15h	/
1	The project and the structure was created	root	5068d 11h	/