URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] - Rev 18

Rev	Log message	Author	Age	Path
18	A bunch of synthesis error/warning removed. Master and analyzer synthesis OK on Spartan6 FPGA	acapola	4850d 08h	/
17	yet another fix of the analyzer: ATR, and convention handling	acapola	4867d 07h	/
16	just cosmetic	acapola	4871d 07h	/
15	tpdu level tasks inverse convention	acapola	4872d 06h	/
14	Task to send strings as bytes improved	acapola	4875d 05h	/
13	Corrections in analyzer to handle TDi and historical bytes in ATR and PPS todo: handle inverse convention	acapola	4876d 08h	/
12	pps sequence added to test bench endOfTx added to TxCore	acapola	4887d 05h	/
11	added BSD licence header to files	acapola	4887d 09h	/
10	communication direction probe added	acapola	4887d 10h	/
9	parity convention fixed	acapola	4893d 06h	/
8		acapola	4895d 05h	/
7	- rx/tx use "cyclesPerEtu" input - "stopBit" status bit timing fixed - analyzer: "lastByte" and "bytesCnt" functional	acapola	4896d 05h	/
6	analyzer added to test bench, not functional yet...	acapola	4897d 05h	/
5	draft of t=0 protocol analyzer (to ease debuging, and eventually as an ip itself)	acapola	4898d 05h	/
4	Basic test bench completed for T=0: a card send ATR, reader send a command TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)	acapola	4899d 06h	/
3	initial draft, not functional yet	acapola	4906d 07h	/
2		acapola	4906d 08h	/
1	The project and the structure was created	root	4907d 04h	/