OpenCores
URL https://opencores.org/ocsvn/jart/jart/trunk

Subversion Repositories jart

[/] - Rev 75

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
75 + Optimized fitting values. jguarin2002 5512d 11h /
74 stupid typo.... jguarin2002 5512d 12h /
73 + GPL License Added..... jguarin2002 5512d 12h /
72 + Optimized in size.
+ Added the GPL license (which is mandatory!)
+ Added a minimal explanation of how to use the RTL.		 jguarin2002 5512d 12h /
71 Well this is not going to be needed any more. jguarin2002 5512d 13h /
70 Ray Traversal Unitary Vector Component Z in A(7,10) fixed format. The output is the 10 bits of the decimal part.

ok.		 jguarin2002 5514d 12h /
69 Sqrt Error : around 6 %.
Great!		 jguarin2002 5515d 02h /
68 A 4 pipe x 1 clock, square root of variable width from 4 to 4n.

SOOOOOO Beta.		 jguarin2002 5515d 04h /
67 mistypings... jguarin2002 5521d 12h /
66 mistypings... jguarin2002 5521d 12h /
65 The Sphere register block RTL's. jguarin2002 5521d 12h /
64 Sphere Register Block now supported.

The sphere register block has 6 modes of operation:

1. OP1, SZALFA: In this mode we summon out from the register block ONE sphere tuple: Position X,Y,Z and sphere K, per enabled clock cycle. Size of the register allows 4096
spheres.

2. OP1, SZBETA: Same as the above but the allowed spheres are 2048.

3. OP2, SZALFA: In this mode we summon out from the register block TWO spheres tuples: Position X,Y,Z and sphere K, per enabled clock cycle. Size of the register allows 4096
spheres.

4. OP2, SZBETA: Same as the above but the allowed spheres are 2048.

5. OP4, SZALFA: In this mode we summon out from the register block FOUR sphere tuples: Position X,Y,Z and sphere K, per enabled clock cycle. Size of the register allows 4096
spheres.

6. OP4, SZBETA: Same as the above but the allowed spheres are 2048.		 jguarin2002 5521d 12h /
63 By default dont register the V output. jguarin2002 5521d 13h /
62 Minor corrections, cuts and additions. jguarin2002 5522d 16h /
61 Code corrections and few port additions. jguarin2002 5522d 16h /
60 Some K or VD bits are getting are inverted at the exit....

I check the rtl net viewer, and the circuit compiled is quite strange nor correspondant....		 jguarin2002 5523d 07h /
59 scanFF syntax error. jguarin2002 5524d 12h /
58 Add the scanff component declaration. jguarin2002 5524d 12h /
57 RS232 Serial interface aimed to work at 460,8 kbps. jguarin2002 5524d 12h /
56 A Scan Out flip flop used by the dComparisonCell. jguarin2002 5524d 12h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.