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Rev Log message Author Age Path
42 test bench 1 regenerated with new template
added a test for 'long' intr pulses
ja_rd 5612d 00h /
41 test bench 0 regenerated with new template
no changes to the test code
ja_rd 5612d 00h /
40 test bench template now can simulate intr pulses longer than 1 cycle ja_rd 5612d 00h /
39 fixed: int request (intr) can now be wider than 1 cycle ja_rd 5612d 00h /
38 pin assignment for IMSAI demo removed ja_rd 5612d 00h /
37 IMSAI monitor demo removed ja_rd 5612d 00h /
36 CPM demo on cyclone 2 starter board
(work in progress)
ja_rd 5612d 00h /
35 CPM demo pin assignment file (Altera Quartus II) ja_rd 5612d 00h /
34 rs232 sanitized and parametrized ja_rd 5612d 00h /
33 Added old uploaded documents to new repository. root 5742d 14h /
32 Added old uploaded documents to new repository. root 5743d 04h /
31 New directory structure. root 5743d 04h /
30 hexconv.pl nmoved to /asm, where it is actually used ja_rd 5763d 09h /
29 File list updated with new files ja_rd 5763d 09h /
28 These CP/M assembler output files are no longer used
because CP/M assembler is no longer used
ja_rd 5763d 09h /
27 Brief instructions for batch script ja_rd 5763d 10h /
26 Builds test bench from vhdl template and assembly source
relies on TASM to do the assembly
ja_rd 5763d 10h /
25 Moved from /util
Added comments and generally improved options
ja_rd 5763d 10h /
24 Totally changed -- tests interrupts using simulated interrupt controller in hdl test bench
Code reformatted for TASM
ja_rd 5763d 10h /
23 Code reformatted for TASM ja_rd 5763d 10h /

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