URL https://opencores.org/ocsvn/lq057q3dc02/lq057q3dc02/trunk

Subversion Repositories lq057q3dc02

[/] - Rev 36

Rev	Log message	Author	Age	Path
36	converted dcm_sys_to_lcd source file from verilog to VHDL so users don't have to have mixed-language simulation support. Aren't I so nice?? ;-)	jwdonal	5742d 02h	/
35	fixed spelling error	jwdonal	5742d 03h	/
34	fixed syntax	jwdonal	5742d 03h	/
33	added cvs edit feature	jwdonal	5742d 03h	/
32	initial rev	jwdonal	5742d 03h	/
31	moved to new location	jwdonal	5742d 03h	/
30	initial rev	jwdonal	5742d 03h	/
29	initial rev	jwdonal	5742d 03h	/
28	initial rev	jwdonal	5742d 05h	/
27	comments	jwdonal	6049d 21h	/
26	* empty log message *	jwdonal	6256d 20h	/
25	* empty log message *	jwdonal	6256d 20h	/
24	Fixed order of operations	jwdonal	6256d 20h	/
23	Added note on changing project directory names.	jwdonal	6256d 21h	/
22	New source files directory.	jwdonal	6256d 21h	/
21	Changed source files directory name. Necessary for proper simulation results do to XCO files remembering the COE file search path.	jwdonal	6256d 21h	/
20	Changed coefficiecint (COE) files search path	jwdonal	6256d 21h	/
19	* empty log message *	jwdonal	6256d 21h	/
18	Modified coefficient files search path.	jwdonal	6256d 21h	/
17	* empty log message *	jwdonal	6267d 08h	/