URL https://opencores.org/ocsvn/m1_core/m1_core/trunk

Subversion Repositories m1_core

[/] - Rev 34

Rev	Log message	Author	Age	Path
34	Added all the new files for Wishbone peripherals	fafa1971	5842d 07h	/
33	Added files from Mistral's new world	fafa1971	5842d 07h	/
32	Moved files from m1_cpu to m1_core dir	fafa1971	5842d 07h	/
31	New world for Mistral	fafa1971	5842d 07h	/
30	First version with functional verification results.	fafa1971	5919d 05h	/
29	Using code.txt from hello.c	fafa1971	5927d 01h	/
28	Changed NOR operator from (a~\|b) to ~(a\|b)	fafa1971	5927d 06h	/
27	Corrected problems with synthesis and removed system control registers	fafa1971	5933d 05h	/
26	Changed blocking / non-blocking assignments for MUL and DIV requests	fafa1971	5933d 05h	/
25	For now the top-level for synthesis is just m1_cpu	fafa1971	5933d 05h	/
24	Corrected include dirs	fafa1971	5933d 05h	/
23	New script using the correct command file for synthesis with Xilinx ISE WebPack	fafa1971	5933d 05h	/
22	Added script file for synthesis with Xilinx ISE WebPack	fafa1971	5933d 05h	/
21	First revision (you should substitute '~' char with real path).	fafa1971	5939d 23h	/
20	Used only lower bits also for SRAV instruction.	fafa1971	5958d 11h	/
19	Added changes suggested by Paolo Piscopo & Simone Lunardo to fix the bugs they found.	fafa1971	5968d 06h	/
18	Limited range of SHAMT (shift amount) to be only 5 bits ([4:0])	fafa1971	5968d 07h	/
17	Added functional verification tests written by Simone Lunardo & Paolo Piscopo.	fafa1971	5968d 07h	/
16	Corrected some bugs found by Simone Lunardo and Paolo Piscopo.	fafa1971	6012d 05h	/
15	Added default case for ALU.	fafa1971	6012d 06h	/