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Rev Log message Author Age Path
9 Modified next state logic to avoid gated clock on net clock_zero_en_0000 during bitgen process. As a default case the counter enables are de-asserted. thiagu_comp 5801d 12h /
8 Removed old singleDouble and added .ucf kingmu 5804d 13h /
7 Added new singleDouble files kingmu 5804d 14h /
6 Branching trunk to experiment with new singleDouble module kingmu 5804d 14h /
5 Tagging 1.0 release kingmu 5804d 23h /
4 Updated simulation files to reflect new module names kingmu 5809d 19h /
3 Renamed files/modules. Added documentation. kingmu 5809d 19h /
2 initial commit kingmu 5810d 20h /
1 The project was created and the structure was created root 5817d 11h /

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