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Rev Log message Author Age Path
11 changed ROM memory model to synchronous mikel262 6718d 02h /
10 + moved memory allocation request to where it should be
+ reduced latency to 104 cycles
mikel262 6719d 04h /
9 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_2'. 6721d 15h /
8 Updated DOC mikel262 6721d 15h /
7 documentation update. minor area optimization. mikel262 6722d 02h /
6 minor updates mikel262 6723d 02h /
5 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_1'. 6723d 03h /
4 area optimization - 100 slices less mikel262 6723d 03h /
3 This commit was manufactured by cvs2svn to create tag 'MDCT_B10'. 6723d 15h /
2 Initial import (Beta Release) mikel262 6723d 15h /
1 Standard project directories initialized by cvs2svn. 6723d 15h /

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