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25 Added old uploaded documents to new repository. root 5731d 07h /
24 New directory structure. root 5731d 07h /
23 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_8'. 5733d 13h /
22 project released under LGPL mikel262 5733d 13h /
21 Fix for XST synthesis error and improve readibility (by Andreas Bergmann). mikel262 5733d 14h /
20 Fix for XST synthesis error and improve readibility (by Andreas Bergman). mikel262 5733d 14h /
19 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_6'. 6758d 10h /
18 Minor fixes. This release is FPGA proven. mikel262 6758d 10h /
17 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_5'. 6780d 06h /
16 Documentation update, minor fixes mikel262 6780d 06h /
15 Redesigned. Fully pipelined, always ready for data design mikel262 6780d 07h /
14 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_4'. 6784d 06h /
13 performance improved by 8%, latency reduced to 94 cycles mikel262 6784d 06h /
12 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_3'. 6785d 06h /
11 changed ROM memory model to synchronous mikel262 6785d 06h /
10 + moved memory allocation request to where it should be
+ reduced latency to 104 cycles
mikel262 6786d 08h /
9 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_2'. 6788d 19h /
8 Updated DOC mikel262 6788d 19h /
7 documentation update. minor area optimization. mikel262 6789d 05h /
6 minor updates mikel262 6790d 06h /

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