URL https://opencores.org/ocsvn/minimips_superscalar/minimips_superscalar/trunk

Subversion Repositories minimips_superscalar

[/] - Rev 34

Rev	Log message	Author	Age	Path
34	Delete delay_gate to upload a new one.	mcafruni	1706d 00h	/
33	New syscop.vhd	mcafruni	1706d 00h	/
32	Delete syscop to upload a new one.	mcafruni	1706d 00h	/
31	New top module.	mcafruni	1706d 00h	/
30	Delete top module to upload a new one.	mcafruni	1706d 00h	/
29	New banc register file.	mcafruni	1706d 00h	/
28	Delete banc.vhd to upload a new one.	mcafruni	1706d 00h	/
27	New bench on P1 tag.	mcafruni	1706d 00h	/
26	Delete bench to upload a new one.	mcafruni	1706d 00h	/
25	New bench	mcafruni	1706d 01h	/
24	Delete bench to upload a new one.	mcafruni	1706d 01h	/
23	Moving the benchmarks folder into the trunk folder.	mcafruni	1711d 19h	/
22	Wrong code. (fi0.bin) But revealed a bug that needs attention.	mcafruni	1711d 19h	/
21	Correcting codes that work in behavioral simulation but cause problems with implementation. There must be more to be corrected yet. In analysis ...	mcafruni	1711d 19h	/
20	I've uncommented wait statement so that the benchmark to be loaded into the simulation.	mcafruni	1746d 07h	/
19		mcafruni	2079d 23h	/
18	clock_gate.vhd: removed. minimips.vhd: Clock2 input is wrongly connected to the clock signal (Do not ask me how that happened. I'm sorry.). The right thing is to be connected to the clock2 signal. Adjusted.	mcafruni	2080d 00h	/
17	Removing unnecessary clock-gate architecture.	mcafruni	2080d 01h	/
16	FIR filter with 36 coefficients. (binary to run)	mcafruni	2113d 09h	/
15	FIR filter with 36 coefficients.	mcafruni	2113d 09h	/