URL https://opencores.org/ocsvn/minimips_superscalar/minimips_superscalar/trunk

Subversion Repositories minimips_superscalar

[/] - Rev 37

Rev	Log message	Author	Age	Path
37	pc update.	mcafruni	1684d 03h	/
36	update pc	mcafruni	1684d 03h	/
35	New delay_gate.vhd	mcafruni	1686d 22h	/
34	Delete delay_gate to upload a new one.	mcafruni	1686d 23h	/
33	New syscop.vhd	mcafruni	1686d 23h	/
32	Delete syscop to upload a new one.	mcafruni	1686d 23h	/
31	New top module.	mcafruni	1686d 23h	/
30	Delete top module to upload a new one.	mcafruni	1686d 23h	/
29	New banc register file.	mcafruni	1686d 23h	/
28	Delete banc.vhd to upload a new one.	mcafruni	1686d 23h	/
27	New bench on P1 tag.	mcafruni	1686d 23h	/
26	Delete bench to upload a new one.	mcafruni	1686d 23h	/
25	New bench	mcafruni	1686d 23h	/
24	Delete bench to upload a new one.	mcafruni	1686d 23h	/
23	Moving the benchmarks folder into the trunk folder.	mcafruni	1692d 17h	/
22	Wrong code. (fi0.bin) But revealed a bug that needs attention.	mcafruni	1692d 17h	/
21	Correcting codes that work in behavioral simulation but cause problems with implementation. There must be more to be corrected yet. In analysis ...	mcafruni	1692d 17h	/
20	I've uncommented wait statement so that the benchmark to be loaded into the simulation.	mcafruni	1727d 06h	/
19		mcafruni	2060d 22h	/
18	clock_gate.vhd: removed. minimips.vhd: Clock2 input is wrongly connected to the clock signal (Do not ask me how that happened. I'm sorry.). The right thing is to be connected to the clock2 signal. Adjusted.	mcafruni	2060d 22h	/