| Rev |
Log message |
Author |
Age |
Path |
| 104 |
Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools) |
rfajardo |
4953d 07h |
/ |
| 103 |
But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. |
rfajardo |
4955d 22h |
/ |
| 102 |
GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. |
rfajardo |
4955d 22h |
/ |
| 101 |
Documentation, wiki's address updated. |
rfajardo |
4981d 10h |
/ |
| 100 |
syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. |
rfajardo |
4990d 08h |
/ |
| 99 |
backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. |
rfajardo |
4990d 08h |
/ |
| 98 |
Removing deprecated minsoc_top.qsf file. |
rfajardo |
4990d 08h |
/ |
| 97 |
As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. |
rfajardo |
4990d 08h |
/ |
| 96 |
Some files needed for Altera synthesis |
javieralso |
4990d 19h |
/ |
| 95 |
Makefile for Altera FPGAs fixed |
javieralso |
4991d 22h |
/ |
| 94 |
Fix bug in minsoc_top.prj for Altera synthesis |
javieralso |
4994d 07h |
/ |
| 93 |
Support for Altera synthesis. It needs some tune, but it works fine |
javieralso |
4994d 10h |
/ |
| 92 |
backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. |
rfajardo |
4995d 08h |
/ |
| 91 |
prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. |
rfajardo |
4995d 09h |
/ |
| 90 |
After minsoc_top.prj update, make regenerated src and xst files. |
rfajardo |
4996d 00h |
/ |
| 89 |
minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. |
rfajardo |
4996d 00h |
/ |
| 88 |
Project structure, Xilinx Makefiles and simulation working. |
rfajardo |
4996d 00h |
/ |
| 87 |
Synchronizing scripts to behave exactly the same. |
rfajardo |
4996d 02h |
/ |
| 86 |
Updating configure script messages. |
rfajardo |
4996d 02h |
/ |
| 85 |
Central project definition under prj. Synthesis and simulation take their project files from here. |
rfajardo |
4996d 02h |
/ |
