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Rev	Log message	Author	Age	Path
14	Wishbone error signal of Ethernet core was not tied to ground if Ethernet was disabled. Solved now.	rfajardo	5501d 01h	/
13	Updating spartan3e_starter_kit.ucf so that it does not deliver errors on mapping. Moreover it has been changed to off the shelf only have uart support. Ethernet support and generic JTAG can be added by uncommenting the corresponding lines.	rfajardo	5502d 01h	/
12	1) spi_top.v: -TX_NEGEDGE bug reported and recommended solution by Blaise Gassend. (Thank you) 2) minsoc howto extended to: -synthesis of minsoc for Spartan3E Starter Kit with Ethernet 3) spartan3e_starter_kit.ucf changed: -it had problems regarding pin definitions and IO logic types for mapping and place&route. Working flawless now.	rfajardo	5504d 16h	/
11	External interrupt processing was being run multiple times because: -external level interrupts have to be cleared -internal interrupt status register has to be cleared Since internal interrupt status register was being cleared before external level interrupts clearance, these internal interrupt status was being overwritten inbetween. Solution: -move status register reset to end of interrupt handler instead of beginning. Testbench signal uart_srx initialized now.	rfajardo	5511d 20h	/
10	Added a file containing models for each FPGA memory instances used in or1200. The file is in bench/verilog/sim_lib/fpga_memory_primitives.v. With it, people who change the or1200_defines.v inside of the project structure will still be able to simulate, using house-made models, not from manufacturers. minsoc_bench.v had to be extended by the task, init_fpga_memory, to initialize the dual or two port memories instances of or1200. This has to be done based on the type of memory used, so many different instantiations based on definitions. Somehow or1200 expects all memory values to be 0 upon start, so this is necessary.	rfajardo	5525d 20h	/
9	Tiny change to testbench gain: -uart_srx is now reg for future testbench serial input to SoC.	rfajardo	5527d 18h	/
8	Cosmetic changes to minsoc_bench.v: -reset and clock initialization are included into the main initial block, it had an own block before	rfajardo	5527d 18h	/
7	Some changes: -wb_cabs removed from minsoc_top.v and minsoc_tc_top.v -added reset polarity control to minsoc_defines.v through: -POSITIVE_RESET -NEGATIVE_RESET -minsoc_onchip_ram_top.v does not use minsoc_onchip_ram.v oe signals (output enable) anymore, which are implemented as tristate buffers. Now minsoc_onchip_ram_top.v has a generated MUX, which has an arbitrary number of inputs and 1 output. Input are the internal output of the onchip_rams, output the wb_dat_o.	rfajardo	5532d 19h	/
6	No implementation relevant changes. Testbench used generic memory from minsoc_onchip_ram.v has been changed to reflect the correct model of the FPGA's onchip rams: address register and write accesses are sensitive to rising clock edge. Documentation updated to reflect another trial and next steps to speed up the memory access from 2 clocks to 1. The negated clock approach is not standard. The right way to do it would be to use the wishbone signals cti and bte and change the minsoc_onchip_ram_top.v.	rfajardo	5537d 01h	/
5	vpi path corrected in how to.	rfajardo	5543d 00h	/
4	minsoc_bench.v had a big memory declaration to load the firmware, which was not necessary. jp-io-vpi.vpi has to be compiled for different systems so removed from the project. Documentation now explains how to do it. Documentation now includes: -vpi module compilation -gdb patch for adv_jtag_bridge -ideas for future work on minsoc (To Do v.2)	rfajardo	5543d 01h	/
3	Changed documentation -advice to compile sw/utils before compiling target software	rfajardo	5546d 23h	/
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5546d 23h	/
1	The project was created and the structure was created	root	5547d 01h	/

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