OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] - Rev 7

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
7 Some changes:
-wb_cabs removed from minsoc_top.v and minsoc_tc_top.v
-added reset polarity control to minsoc_defines.v through:
-POSITIVE_RESET
-NEGATIVE_RESET
-minsoc_onchip_ram_top.v does not use
minsoc_onchip_ram.v oe signals (output enable) anymore,
which are implemented as tristate buffers. Now
minsoc_onchip_ram_top.v has a generated MUX, which
has an arbitrary number of inputs and 1 output.
Input are the internal output of the onchip_rams,
output the wb_dat_o.		 rfajardo 5558d 22h /
6 No implementation relevant changes.

Testbench used generic memory from minsoc_onchip_ram.v has been changed to reflect the correct model of the FPGA's onchip rams: address register and write accesses are sensitive to rising clock edge.

Documentation updated to reflect another trial and next steps to speed up the memory access from 2 clocks to 1. The negated clock approach is not standard. The right way to do it would be to use the wishbone signals cti and bte and change the minsoc_onchip_ram_top.v.		 rfajardo 5563d 04h /
5 vpi path corrected in how to. rfajardo 5569d 03h /
4 minsoc_bench.v had a big memory declaration to load the firmware, which was not necessary.

jp-io-vpi.vpi has to be compiled for different systems so removed from the project. Documentation now explains how to do it.

Documentation now includes:
-vpi module compilation
-gdb patch for adv_jtag_bridge
-ideas for future work on minsoc (To Do v.2)		 rfajardo 5569d 04h /
3 Changed documentation
-advice to compile sw/utils before compiling target software		 rfajardo 5573d 02h /
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit		 rfajardo 5573d 02h /
1 The project was created and the structure was created root 5573d 04h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.