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Rev Log message Author Age Path
37 Replaced VHDL Header RAM with Verilog, initialized via readmemh from hex file. mikel262 5749d 17h /
36 Fixed RLE ZRL bug. Added Chrominance Huffman tables. Fixed num encoded bytes bug. mikel262 5751d 13h /
35 Added check for image width in testbench. mikel262 5752d 02h /
34 Moved Quantizer to separate pipeline stage to balance processing chain load. mikel262 5752d 10h /
33 mikel262 5752d 18h /
32 mikel262 5753d 14h /
31 Specification update, minor area improvements in BUF_FIFO. mikel262 5756d 15h /
30 mikel262 5757d 03h /
29 mikel262 5757d 11h /
28 BU_FIFO SUB_RAM is now monolithic single block used by all SubFIFO - effect much less memory block usage. mikel262 5757d 11h /
27 mikel262 5760d 00h /
26 mikel262 5760d 00h /
25 moved from branch to trunk mikel262 5760d 00h /
24 mikel262 5760d 00h /
23 mikel262 5761d 11h /
22 Changed divider to use reciprocal lookup table. Improved Huffman processing time. BUF_FIFO almost full signal modified. mikel262 5762d 12h /
21 Huffman.vhd processing latency shortened. mikel262 5763d 11h /
20 Added compressed JPEG output file from testbench mikel262 5763d 12h /
19 Timing improved in MDCT and in Huffman mikel262 5763d 14h /
18 Huffman old design restored. Simulation HOWTO added. mikel262 5763d 14h /

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