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Rev Log message Author Age Path
39 bug fix. mikel262 5721d 05h /
38 Reduced processing latency of Huffman encoding mikel262 5746d 05h /
37 Replaced VHDL Header RAM with Verilog, initialized via readmemh from hex file. mikel262 5750d 09h /
36 Fixed RLE ZRL bug. Added Chrominance Huffman tables. Fixed num encoded bytes bug. mikel262 5752d 05h /
35 Added check for image width in testbench. mikel262 5752d 18h /
34 Moved Quantizer to separate pipeline stage to balance processing chain load. mikel262 5753d 02h /
33 mikel262 5753d 11h /
32 mikel262 5754d 06h /
31 Specification update, minor area improvements in BUF_FIFO. mikel262 5757d 07h /
30 mikel262 5757d 19h /
29 mikel262 5758d 03h /
28 BU_FIFO SUB_RAM is now monolithic single block used by all SubFIFO - effect much less memory block usage. mikel262 5758d 03h /
27 mikel262 5760d 16h /
26 mikel262 5760d 16h /
25 moved from branch to trunk mikel262 5760d 16h /
24 mikel262 5760d 17h /
23 mikel262 5762d 03h /
22 Changed divider to use reciprocal lookup table. Improved Huffman processing time. BUF_FIFO almost full signal modified. mikel262 5763d 04h /
21 Huffman.vhd processing latency shortened. mikel262 5764d 03h /
20 Added compressed JPEG output file from testbench mikel262 5764d 04h /

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