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Rev Log message Author Age Path
43 stall readded mikel262 5456d 21h /
42 Added backpressure/stallability of output interface. mikel262 5460d 08h /
41 Fixed RLE ZRL bug occurring at end of 8x8 block mikel262 5597d 20h /
40 Fixed few bugs in BUF_FIFO and RLE encoder. mikel262 5640d 11h /
39 bug fix. mikel262 5643d 09h /
38 Reduced processing latency of Huffman encoding mikel262 5668d 09h /
37 Replaced VHDL Header RAM with Verilog, initialized via readmemh from hex file. mikel262 5672d 13h /
36 Fixed RLE ZRL bug. Added Chrominance Huffman tables. Fixed num encoded bytes bug. mikel262 5674d 09h /
35 Added check for image width in testbench. mikel262 5674d 22h /
34 Moved Quantizer to separate pipeline stage to balance processing chain load. mikel262 5675d 06h /
33 mikel262 5675d 15h /
32 mikel262 5676d 10h /
31 Specification update, minor area improvements in BUF_FIFO. mikel262 5679d 11h /
30 mikel262 5679d 23h /
29 mikel262 5680d 07h /
28 BU_FIFO SUB_RAM is now monolithic single block used by all SubFIFO - effect much less memory block usage. mikel262 5680d 07h /
27 mikel262 5682d 20h /
26 mikel262 5682d 20h /
25 moved from branch to trunk mikel262 5682d 20h /
24 mikel262 5682d 21h /

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