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Rev Log message Author Age Path
54 mikel262 5519d 09h /
53 mikel262 5519d 09h /
52 Redesigned BUF_FIFO.vhd to significantly reduce area utilization.
Only memory optimized version now possible.
mikel262 5519d 09h /
51 fix in buf fifo (synthesis problem) mikel262 5523d 08h /
50 mikel262 5523d 17h /
49 Added 16 bit RGB 565 input format. mikel262 5523d 17h /
48 mikel262 5523d 18h /
47 mikel262 5523d 18h /
46 x1 mikel262 5532d 20h /
45 stall re-added mikel262 5532d 20h /
44 stall re-added mikel262 5532d 20h /
43 stall readded mikel262 5532d 20h /
42 Added backpressure/stallability of output interface. mikel262 5536d 07h /
41 Fixed RLE ZRL bug occurring at end of 8x8 block mikel262 5673d 19h /
40 Fixed few bugs in BUF_FIFO and RLE encoder. mikel262 5716d 10h /
39 bug fix. mikel262 5719d 08h /
38 Reduced processing latency of Huffman encoding mikel262 5744d 08h /
37 Replaced VHDL Header RAM with Verilog, initialized via readmemh from hex file. mikel262 5748d 12h /
36 Fixed RLE ZRL bug. Added Chrominance Huffman tables. Fixed num encoded bytes bug. mikel262 5750d 08h /
35 Added check for image width in testbench. mikel262 5750d 21h /

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