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Rev Log message Author Age Path
56 BUF_FIFO redesign, for memory/performance tradeoff mikel262 5307d 00h /
55 mikel262 5318d 01h /
54 mikel262 5318d 01h /
53 mikel262 5318d 01h /
52 Redesigned BUF_FIFO.vhd to significantly reduce area utilization.
Only memory optimized version now possible.
mikel262 5318d 01h /
51 fix in buf fifo (synthesis problem) mikel262 5322d 00h /
50 mikel262 5322d 09h /
49 Added 16 bit RGB 565 input format. mikel262 5322d 09h /
48 mikel262 5322d 10h /
47 mikel262 5322d 10h /
46 x1 mikel262 5331d 11h /
45 stall re-added mikel262 5331d 12h /
44 stall re-added mikel262 5331d 12h /
43 stall readded mikel262 5331d 12h /
42 Added backpressure/stallability of output interface. mikel262 5334d 23h /
41 Fixed RLE ZRL bug occurring at end of 8x8 block mikel262 5472d 11h /
40 Fixed few bugs in BUF_FIFO and RLE encoder. mikel262 5515d 02h /
39 bug fix. mikel262 5518d 00h /
38 Reduced processing latency of Huffman encoding mikel262 5543d 00h /
37 Replaced VHDL Header RAM with Verilog, initialized via readmemh from hex file. mikel262 5547d 04h /

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