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Rev Log message Author Age Path
69 mikel262 4878d 08h /
68 mikel262 4878d 08h /
67 mikel262 4878d 08h /
66 memory initialization updated mikel262 5014d 09h /
65 Added VHDL equivalent for Verilog's HeaderRAM.v mikel262 5156d 18h /
64 rel with YUV mikel262 5464d 09h /
63 Added YUV input support. mikel262 5466d 04h /
62 mikel262 5507d 08h /
61 Design now uses 4:2:2 chroma subsampling mikel262 5507d 18h /
60 mikel262 5510d 06h /
59 mikel262 5510d 08h /
58 fix for C_EXTRA_LINES=0 mikel262 5510d 08h /
57 default max performance mikel262 5510d 19h /
56 BUF_FIFO redesign, for memory/performance tradeoff mikel262 5510d 19h /
55 mikel262 5521d 20h /
54 mikel262 5521d 20h /
53 mikel262 5521d 20h /
52 Redesigned BUF_FIFO.vhd to significantly reduce area utilization.
Only memory optimized version now possible.
mikel262 5521d 21h /
51 fix in buf fifo (synthesis problem) mikel262 5525d 19h /
50 mikel262 5526d 04h /

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