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Rev Log message Author Age Path
348 Added comment for 32MB and 128MB DDR parts rhoads 5716d 19h /
347 Xilinx ISE Project file rhoads 5716d 19h /
346 Support optional 4KB cache rhoads 5753d 19h /
345 Commented out optional mult speedup rhoads 5757d 16h /
344 Fixed compiler warning rhoads 5757d 16h /
343 Initial working cache rhoads 5757d 16h /
342 Changed simple cache rhoads 5757d 16h /
341 Permit large file transfers when running on windows rhoads 5757d 16h /
340 Get the length of a file rhoads 5757d 16h /
339 Format output of ls rhoads 5757d 16h /
338 Fix filename problem with 9th file in directory rhoads 5757d 16h /
337 Initial attempt at a cache rhoads 5762d 20h /
336 Better support Linux rhoads 5795d 13h /
335 Use enable signal for byte_we rhoads 5804d 14h /
334 Short time for averaging read signal for 12.5 MHz case rhoads 5814d 14h /
333 Updated Altera lpm_ram_dp usage for Cyclone FPGAs rhoads 5814d 14h /
332 Updated Altera lpm_ram_dp rhoads 5814d 14h /
331 Commented out unconnected signals rhoads 5875d 14h /
330 Simplify sscanf() rhoads 5885d 01h /
329 Fix interrupt line comment rhoads 5966d 12h /

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