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Rev Log message Author Age Path
350 root 5576d 23h /
349 Added help text for bootldr target rhoads 5607d 19h /
348 Added comment for 32MB and 128MB DDR parts rhoads 5607d 19h /
347 Xilinx ISE Project file rhoads 5607d 19h /
346 Support optional 4KB cache rhoads 5644d 19h /
345 Commented out optional mult speedup rhoads 5648d 15h /
344 Fixed compiler warning rhoads 5648d 15h /
343 Initial working cache rhoads 5648d 15h /
342 Changed simple cache rhoads 5648d 15h /
341 Permit large file transfers when running on windows rhoads 5648d 15h /
340 Get the length of a file rhoads 5648d 15h /
339 Format output of ls rhoads 5648d 16h /
338 Fix filename problem with 9th file in directory rhoads 5648d 16h /
337 Initial attempt at a cache rhoads 5653d 20h /
336 Better support Linux rhoads 5686d 13h /
335 Use enable signal for byte_we rhoads 5695d 14h /
334 Short time for averaging read signal for 12.5 MHz case rhoads 5705d 13h /
333 Updated Altera lpm_ram_dp usage for Cyclone FPGAs rhoads 5705d 13h /
332 Updated Altera lpm_ram_dp rhoads 5705d 13h /
331 Commented out unconnected signals rhoads 5766d 14h /

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