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Rev Log message Author Age Path
103 Updated documentation to version 1.5 with dual-clock support JonasDC 4139d 22h /
102 Added some extra information for the test generation software JonasDC 4139d 22h /
101 added README file for simulation, minor update for Makefile clean target. JonasDC 4140d 03h /
100 added version 1.0 tag for completeness. This version is the first version that is adapted to the opencores design rules. Also the code is cleaned up. previous tag was incorrect, now updated JonasDC 4158d 10h /
99 removed tag, wrong directory tagged JonasDC 4158d 10h /
98 added version 1.0 tag for completeness. This version is the first version that is adapted to the opencores design rules. Also the code is cleaned up. JonasDC 4158d 10h /
97 changes in makefile, and fifo's are now also in mod_sim_exp library JonasDC 4175d 03h /
96 minor makefile update JonasDC 4176d 03h /
95 new control logic for the core, allow for greater frequencies for the multiplier.
changes:
- autorun_cntrl: the bit selection for the exponents is now implemented with a shift register in stead of a mux. credits to Geoffrey Ottoy for new design structure.
- mont_cntrl: gave the databus from and to the RAM more time to settle. data now has 3 clocks to get to its destination.		 JonasDC 4176d 03h /
94 BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx		 JonasDC 4188d 23h /
93 Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. This version adds support for the AXI4-Lite bus interface. JonasDC 4191d 05h /
92 updated documentation with minor interrupt changes of AXI interface JonasDC 4191d 05h /
91 changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register. JonasDC 4193d 08h /
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 4194d 22h /
89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 4258d 20h /
88 small update on documentation, changed fault in axi control_reg JonasDC 4264d 21h /
87 updated documentation to version 1.4
core now supports the AXI4-Lite bus		 JonasDC 4264d 22h /
86 update on previous JonasDC 4264d 22h /
85 changed so that reset now also affects slave register JonasDC 4264d 22h /
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS		 JonasDC 4266d 07h /

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