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Subversion Repositories mod_sim_exp

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Rev Log message Author Age Path
29 added software for generation of test input for the tesbenches JonasDC 4952d 14h /
28 updated makefile for new pipeline sources JonasDC 4952d 15h /
27 test input values for multiplier_tb JonasDC 4952d 15h /
26 testbench for only the montgommery multiplier JonasDC 4952d 15h /
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline		 JonasDC 4952d 15h /
24 changed names of top-level module to mod_sim_exp_core JonasDC 4956d 00h /
23 added descriptive comments JonasDC 4956d 01h /
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4958d 19h /
21 changed x_i signal to xi JonasDC 4960d 02h /
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules		 JonasDC 4960d 03h /
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic		 JonasDC 4964d 22h /
18 updated stages with comments and renamed some signals for consistency JonasDC 4965d 21h /
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4966d 02h /
16 package with modified generic parameter for register_n JonasDC 4966d 15h /
15 changed generic for register width from n to width for consistency JonasDC 4966d 15h /
14 changed comments, file is now according to OC design rules JonasDC 4966d 16h /
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules		 JonasDC 4966d 16h /
12 updated comments, file is now completely according to design rules JonasDC 4966d 16h /
11 simulation output folder JonasDC 4966d 18h /
10 changed signal input port names to correct name JonasDC 4966d 21h /

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