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39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 4544d 00h /
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4544d 06h /
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4548d 03h /
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.
JonasDC 4548d 23h /
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes
JonasDC 4549d 01h /
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4549d 02h /
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4549d 05h /
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4549d 06h /
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4549d 11h /
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4549d 12h /
29 added software for generation of test input for the tesbenches JonasDC 4550d 01h /
28 updated makefile for new pipeline sources JonasDC 4550d 02h /
27 test input values for multiplier_tb JonasDC 4550d 02h /
26 testbench for only the montgommery multiplier JonasDC 4550d 02h /
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline
JonasDC 4550d 02h /
24 changed names of top-level module to mod_sim_exp_core JonasDC 4553d 11h /
23 added descriptive comments JonasDC 4553d 12h /
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4556d 05h /
21 changed x_i signal to xi JonasDC 4557d 13h /
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules
JonasDC 4557d 13h /

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