URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 59

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Rev	Log message	Author	Age	Path
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4167d 00h	/
58	made fifo full a warning	JonasDC	4170d 01h	/
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4170d 01h	/
56	this is a branch to test performance of a new style of ram	JonasDC	4170d 03h	/
55	updated resource usage in comments	JonasDC	4171d 00h	/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4171d 00h	/
53	correctly inferred ram for altera dual port ram	JonasDC	4171d 07h	/
52	correct inferring of blockram, no additional resources.	JonasDC	4171d 07h	/
51	true dual port ram for xilinx	JonasDC	4171d 08h	/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4171d 08h	/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4183d 03h	/
48	Tag of the starting version of the project	JonasDC	4183d 03h	/
47	added documentation for the IP core.	JonasDC	4251d 08h	/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4251d 08h	/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4251d 08h	/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4255d 01h	/
43	made the core parameters generics	JonasDC	4255d 01h	/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4261d 09h	/
41	removed deprecated files from version control	JonasDC	4261d 09h	/
40	adjusted core instantiation to new core module name	JonasDC	4269d 13h	/

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Subversion Repositories mod_sim_exp

[/] - Rev 59

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