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Rev	Log message	Author	Age	Path
64	added synthesis reports of xilinx and altera	JonasDC	4316d 12h	/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4316d 12h	/
62	not used anymore	JonasDC	4316d 14h	/
61	updated comments, added optional altera constraint	JonasDC	4316d 14h	/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4319d 05h	/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4319d 05h	/
58	made fifo full a warning	JonasDC	4322d 05h	/
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4322d 05h	/
56	this is a branch to test performance of a new style of ram	JonasDC	4322d 08h	/
55	updated resource usage in comments	JonasDC	4323d 05h	/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4323d 05h	/
53	correctly inferred ram for altera dual port ram	JonasDC	4323d 12h	/
52	correct inferring of blockram, no additional resources.	JonasDC	4323d 12h	/
51	true dual port ram for xilinx	JonasDC	4323d 13h	/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4323d 13h	/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4335d 08h	/
48	Tag of the starting version of the project	JonasDC	4335d 08h	/
47	added documentation for the IP core.	JonasDC	4403d 12h	/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4403d 13h	/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4403d 13h	/

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[/] - Rev 64

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