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Rev Log message Author Age Path
92 updated documentation with minor interrupt changes of AXI interface JonasDC 4273d 09h /
91 changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register. JonasDC 4275d 12h /
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 4277d 03h /
89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 4341d 01h /
88 small update on documentation, changed fault in axi control_reg JonasDC 4347d 02h /
87 updated documentation to version 1.4
core now supports the AXI4-Lite bus		 JonasDC 4347d 02h /
86 update on previous JonasDC 4347d 02h /
85 changed so that reset now also affects slave register JonasDC 4347d 02h /
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS		 JonasDC 4348d 11h /
83 now using values from mod_sim_exp_pkg instead of direct entity JonasDC 4350d 12h /
82 added first version of axi-lite interface and testbench for basic axi-lite operations, now under test JonasDC 4367d 08h /
81 updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration JonasDC 4367d 08h /
80 renamed to version 1.1 to follow the versioning system JonasDC 4377d 02h /
79 Tag for version 1.3 (with new ram style JonasDC 4377d 02h /
78 updated documentation with new RAM style information JonasDC 4377d 02h /
77 found fault in code, now synthesizes normally JonasDC 4382d 23h /
76 testbench update JonasDC 4385d 10h /
75 made rw_address a vector of a fixed width JonasDC 4385d 10h /
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 4388d 06h /
73 updated plb interface, mem_style and device generics added JonasDC 4389d 06h /

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