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94 BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx		 JonasDC 4189d 00h /
93 Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. This version adds support for the AXI4-Lite bus interface. JonasDC 4191d 05h /
92 updated documentation with minor interrupt changes of AXI interface JonasDC 4191d 06h /
91 changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register. JonasDC 4193d 09h /
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 4194d 23h /
89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 4258d 21h /
88 small update on documentation, changed fault in axi control_reg JonasDC 4264d 22h /
87 updated documentation to version 1.4
core now supports the AXI4-Lite bus		 JonasDC 4264d 23h /
86 update on previous JonasDC 4264d 23h /
85 changed so that reset now also affects slave register JonasDC 4264d 23h /
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS		 JonasDC 4266d 07h /
83 now using values from mod_sim_exp_pkg instead of direct entity JonasDC 4268d 08h /
82 added first version of axi-lite interface and testbench for basic axi-lite operations, now under test JonasDC 4285d 04h /
81 updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration JonasDC 4285d 04h /
80 renamed to version 1.1 to follow the versioning system JonasDC 4294d 22h /
79 Tag for version 1.3 (with new ram style JonasDC 4294d 22h /
78 updated documentation with new RAM style information JonasDC 4294d 22h /
77 found fault in code, now synthesizes normally JonasDC 4300d 20h /
76 testbench update JonasDC 4303d 07h /
75 made rw_address a vector of a fixed width JonasDC 4303d 07h /

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