| Rev |
Log message |
Author |
Age |
Path |
| 38 |
- added tiny EEP bootloader (boot directly from SPI EEPROM)
- added docufor this new bootlaoder option |
zero_gravity |
3184d 15h |
/ |
| 37 |
- small typo correction (WB boot address) ;) |
zero_gravity |
3185d 16h |
/ |
| 36 |
- added alternative tiny WB bootloader
- USART and TIMER are now also optional
- doc update
- minor optimizations |
zero_gravity |
3185d 16h |
/ |
| 35 |
- bugfix in SFU's "count set bits" function (it was counting the number of cleared bits... ;) )
- modified start-up code for you guys, who want to directly initialize the internal RAM with a program... DO THAT WITH CAUTION!!! |
zero_gravity |
3193d 16h |
/ |
| 34 |
- minor bootloader edits
- updated documentary: more info about shared I/D memory architecture; new tutorial for creating a Wishbone boot ROM
- added rtl folder for wishbone components (only Wishbone memory (e.g. boot ROM) yet) |
zero_gravity |
3194d 14h |
/ |
| 33 |
- modified SFU (and according lib file), functions: bit-rversal, count leading zeros, count set bits, read-back operand
- updated documentary
- small rtl improvements |
zero_gravity |
3207d 13h |
/ |
| 32 |
- small typo in neo430_usart.h print_BIN functions
- minor modification on sfu_test/main.c |
zero_gravity |
3215d 12h |
/ |
| 31 |
- documentary: Added CPU instruction set summary |
zero_gravity |
3215d 13h |
/ |
| 30 |
new processor version!
- reduced IRQ channels from 8 to 4 (sufficient!)
- replaced SFU's swi option with "count set bits" function
- modified bootloader, doc, library files and example projects according to changes
- minor rtl modifications |
zero_gravity |
3219d 13h |
/ |
| 29 |
- documentary update
- modified bootloader (small issues)
- removed clock enable signal from CPU
- CPU register file is now true single-port (less HW requirements, easier control from FSM)
- recompiled version of image generator (for WIN64) |
zero_gravity |
3222d 14h |
/ |
| 28 |
- wishbone interface: device enable flag, timeout enable flag; timeout constrained to 256 cycles (wb_interface.vhd)
- bug-fix in wishbone library (neo430/neo430_wishbone.h)
- minor timer logic improvement (timer.vhd & usart.vhd)
- documentary update (new wishbone control register flags) |
zero_gravity |
3226d 10h |
/ |
| 27 |
- fixed missing rst signal in sensitivity list (neo430.vhd)
- merged spi and uart libraies together in one lib file (neo430/neo430_usart.h) |
zero_gravity |
3226d 13h |
/ |
| 26 |
- updated ALL file headers again ;D |
zero_gravity |
3227d 14h |
/ |
| 25 |
- new rtl version! less f_max, but also less cycles per instruction; in total: ~15% gain of performance
- updated doc (accurate execution cycles modified)
- small bug-fix in timer_simple example program |
zero_gravity |
3227d 14h |
/ |
| 24 |
- small bug-fix in pio.h library |
zero_gravity |
3228d 10h |
/ |
| 23 |
- added new license header to ALL files ;)
- now using async reset internally (less HW required in some cases)
- minor rtl modifications |
zero_gravity |
3234d 17h |
/ |
| 22 |
- rtl improvements (anderror correction ;) )
- updated doc
- improved compilation scripts
- optimized NEO430 libraries
- just one VHDL package file for complete processor |
zero_gravity |
3242d 17h |
/ |
| 21 |
- IMPORTANT BUG-FIX in cpu's control unit
- fixed mac16.vhd
- updated documentary
- lots of sw improvements
- hw improvements |
zero_gravity |
3247d 15h |
/ |
| 20 |
- error correction in doc
- modified linux makefile and lib include paths in example programs for better linux/win compatibility
- optimized hardware of CPU's control unit |
zero_gravity |
3267d 15h |
/ |
| 19 |
- fixed some alignment errors is doc pdf |
zero_gravity |
3276d 15h |
/ |
