| Rev |
Log message |
Author |
Age |
Path |
| 48 |
HUGE update ;)
- rtl: severe bug fixed in core's interrupt control logic
- rtl: chnaged prescaler selection for TIMER and USART.spi
- sw: bootloaders updated
- sw: example programs updated
- doc: updated, added chapter about interrupts
- rtl: new sw_pwm image in example wishbone RAM/ROM |
zero_gravity |
3109d 03h |
/ |
| 47 |
- new HW version (!):
- removed single-pin pin-change interrupt of PIO module (only one general pin-change IRQ now)
- optimized register file (PC) (less HW required)
- adapted libs and demo programs according to HW changes (PIO module registers and bits)
- modified DOC (PIO chapter) |
zero_gravity |
3112d 04h |
/ |
| 46 |
- bug-fix in boot ROM size computation |
zero_gravity |
3115d 06h |
/ |
| 45 |
- minor rtl, doc and SW code modifications |
zero_gravity |
3132d 06h |
/ |
| 44 |
- small bug-fix in SW PWM example project |
zero_gravity |
3140d 02h |
/ |
| 43 |
- added software reset to the usart
- the three bootloaders now also perform a soft-reset of the USART at system start-up
- new testbench: outputs UART data to the simulator console
- added new features to the documentry |
zero_gravity |
3144d 02h |
/ |
| 42 |
- small bug-fix in bootloader calling subroutine
- modified make scripts: math.h linking added
- minor rtl optimizations
- minor example code modifications |
zero_gravity |
3182d 09h |
/ |
| 41 |
minor edits!
- removed core_id / num_of_cores generics
- replaced by simple 16-bit user code generic - use it the way u like ;)
- bootloader now also displays user code
- doc updated (the new user code stuff) |
zero_gravity |
3193d 05h |
/ |
| 40 |
- changed base address of boot ROM - now 0xF000
- RAM can now be up to 60kB (instead of 56kB)
- added info about bootloader type to SYSCONFIG
- minor edits... |
zero_gravity |
3194d 03h |
/ |
| 39 |
- modified CPUID registers (CPU-features removed)
- updateddefault bootloader: also shows core id / num of cores now |
zero_gravity |
3198d 23h |
/ |
| 38 |
- added tiny EEP bootloader (boot directly from SPI EEPROM)
- added docufor this new bootlaoder option |
zero_gravity |
3199d 00h |
/ |
| 37 |
- small typo correction (WB boot address) ;) |
zero_gravity |
3200d 01h |
/ |
| 36 |
- added alternative tiny WB bootloader
- USART and TIMER are now also optional
- doc update
- minor optimizations |
zero_gravity |
3200d 01h |
/ |
| 35 |
- bugfix in SFU's "count set bits" function (it was counting the number of cleared bits... ;) )
- modified start-up code for you guys, who want to directly initialize the internal RAM with a program... DO THAT WITH CAUTION!!! |
zero_gravity |
3208d 01h |
/ |
| 34 |
- minor bootloader edits
- updated documentary: more info about shared I/D memory architecture; new tutorial for creating a Wishbone boot ROM
- added rtl folder for wishbone components (only Wishbone memory (e.g. boot ROM) yet) |
zero_gravity |
3208d 23h |
/ |
| 33 |
- modified SFU (and according lib file), functions: bit-rversal, count leading zeros, count set bits, read-back operand
- updated documentary
- small rtl improvements |
zero_gravity |
3221d 23h |
/ |
| 32 |
- small typo in neo430_usart.h print_BIN functions
- minor modification on sfu_test/main.c |
zero_gravity |
3229d 21h |
/ |
| 31 |
- documentary: Added CPU instruction set summary |
zero_gravity |
3229d 22h |
/ |
| 30 |
new processor version!
- reduced IRQ channels from 8 to 4 (sufficient!)
- replaced SFU's swi option with "count set bits" function
- modified bootloader, doc, library files and example projects according to changes
- minor rtl modifications |
zero_gravity |
3233d 22h |
/ |
| 29 |
- documentary update
- modified bootloader (small issues)
- removed clock enable signal from CPU
- CPU register file is now true single-port (less HW requirements, easier control from FSM)
- recompiled version of image generator (for WIN64) |
zero_gravity |
3237d 00h |
/ |
