URL https://opencores.org/ocsvn/next186/next186/trunk

Subversion Repositories next186

[/] - Rev 20

Rev	Log message	Author	Age	Path
20	Implemented the undocumented SALC instructions (SBB AL, AL without affecting the flags) Some speed improvements (separate data/address I/O path)	ndumitrache	2614d 18h	/
19	Add A20 address line	ndumitrache	3835d 15h	/
18	nicer code	ndumitrache	4138d 09h	/
17	fixed OV/CY flags for IMUL	ndumitrache	4146d 16h	/
16	fixed OV/CY flags for IMUL	ndumitrache	4146d 19h	/
15	doc fix	ndumitrache	4160d 10h	/
14	generate invalid opcode exception for MOV FS and GS	ndumitrache	4188d 08h	/
13	fix PUSHA SP pushed stack value, which should be the one before PUSHA	ndumitrache	4196d 19h	/
12	fix IDIV when Q=0	ndumitrache	4231d 12h	/
11	fix RET n alignment bug fix TRAP interrupt acknowledge updated specs	ndumitrache	4238d 19h	/
10	fixed MUL/IMUL 8bit flags bug	ndumitrache	4275d 11h	/
9	fixed DAA,DAS bug	ndumitrache	4293d 14h	/
8	fixed DIV bug (exception on sign bit)	ndumitrache	4337d 13h	/
7	fixed REP CMPS/SCAS bug when interrupted on the <equal> item	ndumitrache	4561d 20h	/
6	updated CMPS/SCAS timing	ndumitrache	4561d 20h	/
5	Fixed CMPS/SCAS bug when interrupted on the <equal> item	ndumitrache	4561d 20h	/
4	comment fix	ndumitrache	4576d 21h	/
3	updated comments	ndumitrache	4626d 20h	/
2	v1.0	ndumitrache	4627d 12h	/
1	The project and the structure was created	root	4627d 18h	/