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Rev Log message Author Age Path
183 Renamed core to o8_cpu to match new naming scheme jshamlet 1699d 16h /
182 Simplified the address generation logic at the expense of making LDX take one additional clock cycle. This allowed the address logic to be split out of the main state machine and simplified (greatly). During this process, a bug in SDO was found and fixed that caused it to return through the wrong pipe fill state wnen auto increment was disabled. jshamlet 1699d 16h /
181 Altered the RSP instruction to allow the stack pointed to either be restored from registers or stored to registers based on the status of a processor bit. Also modified LDX to simplify the address logic. jshamlet 1700d 12h /
180 Added additional Open8 compatible modules jshamlet 1704d 16h /
179 Replacing files accidentally deleted during check-in jshamlet 1714d 12h /
178 Adding Open8 toolset for pure assembly jshamlet 1714d 12h /
177 Fixed comments in RTC module jshamlet 3024d 17h /
176 Fixed documentation errors,
Modified uSec_Tick such that it is always generated regardless of the interval.		 jshamlet 3029d 14h /
175 Added 4 and 8-bit LCD interfaces with backlight and contrast DACs jshamlet 3029d 19h /
174 Added ROM/RAM wrappers jshamlet 3224d 14h /
173 Added a couple of useful interfaces for detecting button presses and clock changes. jshamlet 3224d 14h /
172 General code cleanup jshamlet 3224d 14h /
171 Fixed comments for offsets 0x0 - 0x3 to indicate the read value jshamlet 3224d 14h /
170 Added 24-bit resolution epoch timer / alarm clock jshamlet 3224d 14h /
169 Corrected issue with CMP and SBC generating an inverted carry flag and added new constants to the package file to simplify interfacing new modules. jshamlet 3279d 15h /
168 Simplified write data path logic,
Converted RTC to packed BCD,
Corrected several bugs in real time clock component,		 jshamlet 4058d 11h /
167 Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus.		 jshamlet 4066d 09h /
166 fixed additional issues with range checking on PCREL relocations for open8, added test cases to verify, catch tree up with binutils datestamp 20120301 khays 4630d 10h /
165 fixed issues with PC relative fixups in the linker khays 4631d 17h /
164 Modified the data path to allow the bus to go idle while waiting for an interrupt. This makes it easier to debug code that uses the WAI instruction, as both Wr_Enable and Rd_Enable go low. jshamlet 4702d 05h /

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