OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] - Rev 209

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
209 Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core.		 jshamlet 1699d 21h /
208 Removed unnecessary package references jshamlet 1700d 07h /
207 Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics. jshamlet 1701d 00h /
206 Merged interrupt logic with other clocked process. jshamlet 1704d 19h /
205 More code and comment cleanup for the new SDLC engine jshamlet 1704d 19h /
204 Fixed more incorrect comments jshamlet 1704d 19h /
203 Removed an extra delay FF from the bitclock rising edge signal for the clock slave configuration to better center the rising edge pulse on the receive signal. jshamlet 1705d 01h /
202 Fixed receiver bug that caused false flag detection,
Split the large sdlc_serial_ctrl entity into sub-entities to make debugging easier.		 jshamlet 1705d 02h /
201 Fixed comments regarding RX Checksum location jshamlet 1706d 23h /
200 Renamed dual-port buffer to match other entities. jshamlet 1707d 00h /
199 Added monitor ram for debugging and fixed issue with dual-port read path. jshamlet 1707d 00h /
198 Removed debugging memory jshamlet 1707d 08h /
197 Fixed incorrect comments jshamlet 1707d 08h /
196 Modified the update logic to allow direct writes to offset 0xFE for refreshing the clock status. This way, any write to the clock status register will immediately be undone. (Writing 0x00 to offset 0xFF is once-more ignored) jshamlet 1707d 09h /
195 Added dual-port RAM core for SDLC interface. jshamlet 1708d 03h /
194 Cleaned up licensing sections jshamlet 1708d 03h /
193 Fixed incorrect comment in o8_alu16.vhd. The value of the write to 0x1F doesn't matter, as the write itself triggers the calculation. jshamlet 1708d 04h /
192 Added SDLC packet engine jshamlet 1708d 04h /
191 Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it.		 jshamlet 1708d 04h /
190 Fixed a bug in CPU where RTI/RTS wasn't idling the instruction cache, causing intermittent failures where RTI would execute as RTS, corrupting the stack;
Fixed a bug in the real-time clock where the uSec tick generator would stop if the PIT timer value was left/set to 0x00.		 jshamlet 1720d 02h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.