Rev |
Log message |
Author |
Age |
Path |
223 |
Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up. |
jshamlet |
1559d 23h |
/ |
222 |
Created a modified version of the epoch timer with a 32-bit, 1-uS resolution timer/comparator. |
jshamlet |
1560d 04h |
/ |
221 |
o8_vdsm8.vhd now has a default value assigned at compile time, o8_register.vhd was cleaned up some more. |
jshamlet |
1560d 23h |
/ |
220 |
More revision sections added |
jshamlet |
1560d 23h |
/ |
219 |
Added revision block and corrected creation date. |
jshamlet |
1560d 23h |
/ |
218 |
Revision sections added,
vdsm8.vhd added. |
jshamlet |
1560d 23h |
/ |
217 |
Broke out the vdsm8 as a separate entity, since it is used in several places,
Even MORE code cleanup. |
jshamlet |
1560d 23h |
/ |
216 |
Fixed missing parenthesis |
jshamlet |
1561d 01h |
/ |
215 |
More code cleanup |
jshamlet |
1561d 02h |
/ |
214 |
Initial add of some older code |
jshamlet |
1565d 00h |
/ |
213 |
Code and comment cleanup |
jshamlet |
1565d 00h |
/ |
212 |
Fixed issue with rewritten epoch timer not clearing alarm on set point write. |
jshamlet |
1565d 06h |
/ |
211 |
Ok, this time with feeling. Timer should now properly reset on interval update. |
jshamlet |
1566d 04h |
/ |
210 |
Modified the timers to reset on new interval write. This avoids an issue in the original design where the timer had to reach zero before updating, potentially causing unwanted interrupts.
Also added a flag to the CPU to allow interrupts to be processed sequentially based on the state of the I bit. This one is set to false by default, as it is a significant change in interrupt behavior. Long, and reentrant, ISRs can clear the I bit prematurely to allow themselves to be interrupted.
Lastly, added the I bit to the exported flags for possible use in memory protection schemes. |
jshamlet |
1566d 06h |
/ |
209 |
Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core. |
jshamlet |
1566d 19h |
/ |
208 |
Removed unnecessary package references |
jshamlet |
1567d 04h |
/ |
207 |
Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics. |
jshamlet |
1567d 21h |
/ |
206 |
Merged interrupt logic with other clocked process. |
jshamlet |
1571d 16h |
/ |
205 |
More code and comment cleanup for the new SDLC engine |
jshamlet |
1571d 16h |
/ |
204 |
Fixed more incorrect comments |
jshamlet |
1571d 17h |
/ |