| Rev |
Log message |
Author |
Age |
Path |
| 244 |
Added two new generics to the CPU model. The first is a supervisory mode that disables the STP PSR_I instruction. This prevents errant code execution from setting the I bit, and disabling any subsequent memory protection logic. The second allows the default state of the I bit to be set at startup. If set true, initialization code will run with the I bit set, allowing it to bypass memory protection.
Also modified the RAM models to include write mask logic, where the mask register is write-protected by the I bit in the CPU. When enabled, the models will prevent code from writing to memory regions which do not have their mask bits set. The upshot is that code can effectively "write protect" the RAM - which is useful for multitasking applications.
Also, most modules have been updated with write qualification inputs, allowing a similar scheme to be used for I/O, though not as elegantly. I use a register module, whose own write qual line is attached to the external copy of the I bit as an I/O write protect register.
Lastly, added a new externally triggered timer, which can generate pulses with programmable delays and widths, and which can interrupt on either the input trigger, the output rising edge, or output falling edge. The time base can be either the internal microsecond tick signal, or an external clock. |
jshamlet |
1628d 18h |
/ |
| 243 |
Optimized code to prefer RAM vs register. |
jshamlet |
1635d 22h |
/ |
| 242 |
Added write protect logic to the RAM cores and system timer as part of scheme to keep tasks from messing up the scheduler or other task's memory. The RAM is now divided into regions with a separate write mask register. The write mask register itself is only writeable with the I bit is set (during an interrupt or by setting it using STP PSR_I). The 1K memory is divided into 16, 64 byte regions while the 4K memory is divided into 32, 128 byte regions. The system timer simply checks for the I bit being set when the write protect generic is set.
Note that setting the write_protect generic false, or leaving it unset, will keep the previous behavior. |
jshamlet |
1635d 22h |
/ |
| 241 |
Added an Open8 compatible 7-segment display/decoder and uploaded local/private documentation. |
jshamlet |
1640d 17h |
/ |
| 240 |
Simplified the vector tx/rx system to a single line. An idle detector replaces the attn_req signal. |
jshamlet |
1642d 21h |
/ |
| 239 |
More cleanup and notation of board to board I/O |
jshamlet |
1643d 02h |
/ |
| 238 |
Removed extraneous reference to Ints.VEC_Flag from task.s, since it is supposed to be in the init function in test_fn.s. |
jshamlet |
1643d 21h |
/ |
| 237 |
Found some errors in the comments and cleaned up unnecessary library references. |
jshamlet |
1644d 00h |
/ |
| 236 |
More software cleanup for the Open8_II project |
jshamlet |
1644d 01h |
/ |
| 235 |
Ok, this time with feeling. |
jshamlet |
1648d 19h |
/ |
| 234 |
Forgot to add documentation |
jshamlet |
1648d 21h |
/ |
| 233 |
Updated the Sample Projects.zip |
jshamlet |
1648d 21h |
/ |
| 232 |
More code cleanup on sample projects. SDLC2LCD should now match the Open8_II project model. |
jshamlet |
1658d 01h |
/ |
| 231 |
Updated sample projects and added elapsed time capture (chronometer) module |
jshamlet |
1658d 01h |
/ |
| 230 |
Added two sample projects that show how to connect and program an Open8 system |
jshamlet |
1661d 12h |
/ |
| 229 |
Created a new version of the system timer with 24-bit, 1-uS resolution. The new timer has a much different register interface, so it is now o8_sys_timer_ii. |
jshamlet |
1661d 23h |
/ |
| 228 |
Added an initialization constant for the OPEN8_BUS_TYPE record. |
jshamlet |
1662d 13h |
/ |
| 227 |
Added a demonstration Open8_cfg.vhd file, which is used to configure the system constants. It also provides a function that makes it easy to merge read buses. |
jshamlet |
1662d 20h |
/ |
| 226 |
Forgot the updated package file... |
jshamlet |
1662d 23h |
/ |
| 225 |
Added Halt_Ack to go with Halt_Req. |
jshamlet |
1662d 23h |
/ |
