OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] - Rev 272

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
272 Updated the HTML documentation to reflect the removed generic. jshamlet 1501d 18h /
271 Removed deleted generic define. jshamlet 1501d 18h /
270 Moved CPU internal constants to o8_cpu.vhd and replace the generic that set the RSP direction flag with a constant instead. This removes the need to expose internal architectural flags externally.

Also added a hard-coded version register that takes a major and minor value as bytes using generics. This is a read-only register to the CPU.
jshamlet 1501d 18h /
269 Modified the write data path to use separate enumerated states rather than reuse the .reg field to improve performance. jshamlet 1504d 07h /
268 Added a 16-input external interrupt manager and dedicated SPI tx-only transmitter (for use with DACs, etc.). Also updated the soft-DACs with cleaned up HDL. jshamlet 1504d 08h /
267 Corrected the file description to indicate this is an example package. jshamlet 1504d 08h /
266 Accidentally uploaded incorrect example file for Open8_cfg.vhd jshamlet 1504d 08h /
265 Fixed a bug where "reg" wasn't being initialized with Poly_Init at reset. jshamlet 1596d 17h /
264 Updated comments jshamlet 1606d 14h /
263 Fixed a very old bug in the CPU core where autoincrements weren't affecting the upper register in the pair, causing it to loop around the lower 256 bytes. This only affected LDX/LDO, as the proper ALU signals were being generated in STO/STX and UPP. Wow, that bug has been in there for AGES.

Also separated the SDLC TX and RX interrupts so that they could be handled separately.
jshamlet 1606d 14h /
262 Added comments to LCD controllers - specifically that reading either register 0 or 1 will return the ready status. This code was already present, but not mentioned in the register map. jshamlet 1615d 18h /
261 Increased delay timer to 7 bits for button press detection. jshamlet 1622d 18h /
260 Added missing comments for Sequential_Interrupts generic, as well as comments explaining portions of the CPU operations. jshamlet 1635d 17h /
259 Fixed issue where Write_Fault wasn't defaulting to '0' when Write_Protect was set to FALSE,
Added a pulse interval measurement entity,
Fixed comments.
jshamlet 1635d 18h /
258 Fixed write bug in o8_ltc2355_2p.vhd, added a newer Open8_cfg.vhd, and the sys_tick.vhd utility entity. jshamlet 1636d 16h /
257 Fixed misnamed signal in o8_7seg.vhd and added a replacement switch interface that handles both static and pushbutton switches. jshamlet 1636d 17h /
256 Removed unused generic from the status_led.vhd and cleaned up comments on the CPU jshamlet 1636d 18h /
255 Modified code to make ModelSim happy (It didn't like the generate blocks for some reason). Also added a block describing the new generic. jshamlet 1636d 22h /
254 Simplified the ISR address logic so that the upper 12 bits are constant (set by generic) and only the lower 4 bits are registered/computed. jshamlet 1637d 13h /
253 Fixed spelling error in comment jshamlet 1637d 13h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.