OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] - Rev 285

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
285 Added checksum byte to vector tx/rx to avoid issues with serial line noise glitching the receiver. Also modified the transmitted to take any generic argument, rather than canned arguments. jshamlet 1152d 05h /
284 Corrected the vhdl unit name and description for o8_7seg.vhd jshamlet 1265d 16h /
283 Altered SDLC bitclock check on TX to NOT block when tested by software, but to instead ignore packet write requests if BClk_Okay is low. This allows software to continue checking BClk_Okay in a polling loop. jshamlet 1269d 04h /
282 Modified the SDLC core transmit states to have consistent naming. jshamlet 1269d 04h /
281 Added pre-initialization to the dual-port RAM signals. jshamlet 1269d 07h /
280 Got rid of silly aliases that connected the dual-port memory and the arbitration logic. jshamlet 1269d 07h /
279 More comment cleanup jshamlet 1270d 05h /
278 Flattened the SDLC interface to fewer files and eliminated the package file. jshamlet 1270d 22h /
277 Fixed documentation errors related to flags. The UPP ALU instruction only alters the C flag, not the Z or N flags. This implies that using indexed loads or stores with auto post-increment will potentially alter the C flag. jshamlet 1271d 04h /
276 More comment fixes jshamlet 1306d 01h /
275 Fixed a minor comment error. jshamlet 1307d 19h /
274 Updated comments with more corrections jshamlet 1308d 02h /
273 Updated comments with corrections jshamlet 1308d 04h /
272 Updated the HTML documentation to reflect the removed generic. jshamlet 1318d 03h /
271 Removed deleted generic define. jshamlet 1318d 03h /
270 Moved CPU internal constants to o8_cpu.vhd and replace the generic that set the RSP direction flag with a constant instead. This removes the need to expose internal architectural flags externally.

Also added a hard-coded version register that takes a major and minor value as bytes using generics. This is a read-only register to the CPU.		 jshamlet 1318d 03h /
269 Modified the write data path to use separate enumerated states rather than reuse the .reg field to improve performance. jshamlet 1320d 17h /
268 Added a 16-input external interrupt manager and dedicated SPI tx-only transmitter (for use with DACs, etc.). Also updated the soft-DACs with cleaned up HDL. jshamlet 1320d 17h /
267 Corrected the file description to indicate this is an example package. jshamlet 1320d 17h /
266 Accidentally uploaded incorrect example file for Open8_cfg.vhd jshamlet 1320d 18h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.