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Rev Log message Author Age Path
13 test bench for search_item stvhawes 3454d 22h /
12 wrapper test for search_item stvhawes 3460d 08h /
11 multiplex searh item added stvhawes 3461d 01h /
10 split source files to sime and rtl stvhawes 3475d 00h /
9 highlevel block diagram added stvhawes 3475d 21h /
8 sim sequence error fixed, so 20% success -> 100% success for unit test on fpga stvhawes 3475d 23h /
7 split clock/byte_ready and fix logic stvhawes 3480d 16h /
6 fixing synthesizable stvhawes 3482d 01h /
5 fixing synthesizable stvhawes 3482d 05h /
4 developing ideas around unit test / fpga verification stvhawes 3482d 17h /
3 developing ideas around unit test / fpga verification stvhawes 3482d 17h /
2 initial sources, wrappers for regression test harness stvhawes 3493d 20h /
1 The project and the structure was created root 3495d 14h /

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