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Rev Log message Author Age Path
14 search_item_wrapper bench debugged stvhawes 3473d 17h /
13 test bench for search_item stvhawes 3476d 22h /
12 wrapper test for search_item stvhawes 3482d 07h /
11 multiplex searh item added stvhawes 3483d 00h /
10 split source files to sime and rtl stvhawes 3496d 23h /
9 highlevel block diagram added stvhawes 3497d 20h /
8 sim sequence error fixed, so 20% success -> 100% success for unit test on fpga stvhawes 3497d 22h /
7 split clock/byte_ready and fix logic stvhawes 3502d 15h /
6 fixing synthesizable stvhawes 3504d 00h /
5 fixing synthesizable stvhawes 3504d 04h /
4 developing ideas around unit test / fpga verification stvhawes 3504d 16h /
3 developing ideas around unit test / fpga verification stvhawes 3504d 16h /
2 initial sources, wrappers for regression test harness stvhawes 3515d 19h /
1 The project and the structure was created root 3517d 14h /

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