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Rev Log message Author Age Path
15 adding in search_control and testbench stvhawes 3499d 19h /
14 search_item_wrapper bench debugged stvhawes 3505d 15h /
13 test bench for search_item stvhawes 3508d 20h /
12 wrapper test for search_item stvhawes 3514d 05h /
11 multiplex searh item added stvhawes 3514d 22h /
10 split source files to sime and rtl stvhawes 3528d 21h /
9 highlevel block diagram added stvhawes 3529d 18h /
8 sim sequence error fixed, so 20% success -> 100% success for unit test on fpga stvhawes 3529d 20h /
7 split clock/byte_ready and fix logic stvhawes 3534d 13h /
6 fixing synthesizable stvhawes 3535d 22h /
5 fixing synthesizable stvhawes 3536d 02h /
4 developing ideas around unit test / fpga verification stvhawes 3536d 14h /
3 developing ideas around unit test / fpga verification stvhawes 3536d 14h /
2 initial sources, wrappers for regression test harness stvhawes 3547d 17h /
1 The project and the structure was created root 3549d 11h /

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