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Rev Log message Author Age Path
22 mixed rising_edge / falling_edge logic removed stvhawes 3563d 03h /
21 flakey sim bugs (1/10 test 2 fails) stvhawes 3563d 05h /
20 search_control_sim prepped stvhawes 3570d 00h /
19 search_control is up for simulation (ghdl) - tidied extra testbenches stvhawes 3577d 00h /
18 search_control is up for simulation (ghdl) stvhawes 3577d 00h /
17 persistent bug: search_control_wrapper.vhd:230:21:@36us:(assertion error): search_control_wrapper: test: 3 bad id stvhawes 3582d 11h /
16 minor fixes to search_control test bench stvhawes 3588d 21h /
15 adding in search_control and testbench stvhawes 3590d 01h /
14 search_item_wrapper bench debugged stvhawes 3595d 22h /
13 test bench for search_item stvhawes 3599d 02h /
12 wrapper test for search_item stvhawes 3604d 12h /
11 multiplex searh item added stvhawes 3605d 05h /
10 split source files to sime and rtl stvhawes 3619d 03h /
9 highlevel block diagram added stvhawes 3620d 00h /
8 sim sequence error fixed, so 20% success -> 100% success for unit test on fpga stvhawes 3620d 02h /
7 split clock/byte_ready and fix logic stvhawes 3624d 20h /
6 fixing synthesizable stvhawes 3626d 04h /
5 fixing synthesizable stvhawes 3626d 09h /
4 developing ideas around unit test / fpga verification stvhawes 3626d 21h /
3 developing ideas around unit test / fpga verification stvhawes 3626d 21h /

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