URL https://opencores.org/ocsvn/open_hitter/open_hitter/trunk

Subversion Repositories open_hitter

[/] - Rev 22

Rev	Log message	Author	Age	Path
22	mixed rising_edge / falling_edge logic removed	stvhawes	3418d 13h	/
21	flakey sim bugs (1/10 test 2 fails)	stvhawes	3418d 15h	/
20	search_control_sim prepped	stvhawes	3425d 10h	/
19	search_control is up for simulation (ghdl) - tidied extra testbenches	stvhawes	3432d 09h	/
18	search_control is up for simulation (ghdl)	stvhawes	3432d 10h	/
17	persistent bug: search_control_wrapper.vhd:230:21:@36us:(assertion error): search_control_wrapper: test: 3 bad id	stvhawes	3437d 20h	/
16	minor fixes to search_control test bench	stvhawes	3444d 07h	/
15	adding in search_control and testbench	stvhawes	3445d 11h	/
14	search_item_wrapper bench debugged	stvhawes	3451d 08h	/
13	test bench for search_item	stvhawes	3454d 12h	/
12	wrapper test for search_item	stvhawes	3459d 22h	/
11	multiplex searh item added	stvhawes	3460d 14h	/
10	split source files to sime and rtl	stvhawes	3474d 13h	/
9	highlevel block diagram added	stvhawes	3475d 10h	/
8	sim sequence error fixed, so 20% success -> 100% success for unit test on fpga	stvhawes	3475d 12h	/
7	split clock/byte_ready and fix logic	stvhawes	3480d 06h	/
6	fixing synthesizable	stvhawes	3481d 14h	/
5	fixing synthesizable	stvhawes	3481d 19h	/
4	developing ideas around unit test / fpga verification	stvhawes	3482d 07h	/
3	developing ideas around unit test / fpga verification	stvhawes	3482d 07h	/