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[/] - Rev 9

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Rev Log message Author Age Path
9 highlevel block diagram added stvhawes 3620d 00h /
8 sim sequence error fixed, so 20% success -> 100% success for unit test on fpga stvhawes 3620d 02h /
7 split clock/byte_ready and fix logic stvhawes 3624d 20h /
6 fixing synthesizable stvhawes 3626d 04h /
5 fixing synthesizable stvhawes 3626d 09h /
4 developing ideas around unit test / fpga verification stvhawes 3626d 21h /
3 developing ideas around unit test / fpga verification stvhawes 3626d 21h /
2 initial sources, wrappers for regression test harness stvhawes 3637d 23h /
1 The project and the structure was created root 3639d 18h /

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