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URL https://opencores.org/ocsvn/openarty/openarty/trunk

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[/] - Rev 60

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Rev Log message Author Age Path
60 Bringing the main directory up to date with the github repository dgisselq 2774d 08h /
59 Removed no-longer-used files. dgisselq 2774d 08h /
58 Added the current sim sw back in within the sim subdirectory dgisselq 2774d 08h /
57 Removed the remaining bench/cpp files.

These are moved to the sim/verilator directory.
dgisselq 2774d 08h /
56 Files moved to the new sim directory dgisselq 2774d 08h /
55 Updated the documentation for 8-bit bytes. dgisselq 2774d 08h /
54 Added in a working C-library for the ZipCPU.

Provides stdin/stdout support.
dgisselq 2774d 08h /
53 Removing the artyboard.h file from the dev directory. dgisselq 2774d 08h /
52 Updated sw for the Arty. dgisselq 2774d 08h /
51 Updated host software, following 8-bit byte updates. dgisselq 2774d 08h /
50 Updated the CPU and distribution in general to handle 8-bit bytes. dgisselq 2774d 08h /
49 Moved the location of the ZIPSYSTEM in memory, made the artyboard.h constants
more friendly and more complete, fixed two bugs in the CPU (jumps to breaks,
and s/w clearing of icache), added a NO_USERMODE option to the CPU, and more.
Rebuild any user programs before using this build.
dgisselq 2898d 21h /
48 Greatly expanded the specification, including how to's, getting started guide,
register definitions, etc.
dgisselq 2901d 10h /
47 Updated. dgisselq 2919d 01h /
46 Sped the UART simulator back up to 1MBaud. dgisselq 2919d 01h /
45 Updated the flash, and the flash test bench, for Quad I/O read commands. dgisselq 2919d 01h /
44 Fixed the flash so that it now runs in 1) high speed (41MHz), and 2) that it
doesn't struggle to do read bursts. This should greatly speed up access time.
dgisselq 2919d 01h /
43 Cleaned up the CPU memory documentation. dgisselq 2919d 01h /
42 Fixed up the CPU so that it passes a multiply test bench, in addition to the
CPU test.
dgisselq 2919d 01h /
41 Added the CPU test program to the Arty distribution. This works. dgisselq 2919d 01h /

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