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Rev Log message Author Age Path
13 Here are the updates necessary to get the initial Quad SPI flash driver working.
This includes in particular the bus interconnect (in fastmaster.v), and the
final hookup to the external wires (in fasttop.v).		 dgisselq 3665d 02h /
12 A work in progress. This checkin contains fixes for the flash (mostly),
together with some logic reductions facilitating full speed (200MHz) build.		 dgisselq 3666d 05h /
11 Files necessary to simulate the entire Arty board--everything at the fastmaster
module and below.		 dgisselq 3666d 05h /
10 Updated flash data and test files, for a flash that produces it's answers a
clock after I'm expecting them.		 dgisselq 3666d 05h /
9 Adding copywrite statement (oops). dgisselq 3666d 05h /
8 Fixes the makefile so it builds a complete testbench suite, emulating the
entire Arty board.		 dgisselq 3666d 05h /
7 This implements the coordination of a massive build/test suite--just not the
actual configuration file itself.		 dgisselq 3666d 05h /
6 Minor updates, mostly to support the development of the DDR3 SDRAM--such
as creating addresses for the debugging scope used to figure out what's
going on with it.		 dgisselq 3666d 05h /
5 Initial checkin, this time of the bench testing s/w. dgisselq 3681d 08h /
4 Initial host software pack. dgisselq 3681d 08h /
3 Initial set of files. The flash appears to work, memory hasn't been started,
the MDIO controller works in simulation, etc. Everything below fasttop.v works
at 200MHz (not the CPU---yet).		 dgisselq 3681d 08h /
2 Initial documentation/proposed specification. (I'm writing the spec as I'm
building the core.)		 dgisselq 3682d 03h /
1 The project and the structure was created root 3682d 07h /

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