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Rev Log message Author Age Path
40 Fixed a problem with the declaration of variables to be volatile. dgisselq 2988d 06h /
39 Fixes the OLED test so that it runs using the DMA. dgisselq 2988d 06h /
38 ZipLoad can now load programs to non-reset locations. dgisselq 2988d 06h /
37 Updated documentation and copyright. dgisselq 2988d 06h /
36 Lots of changes, see the git changelog for details. dgisselq 2994d 15h /
35 Added comments and copyright notice. dgisselq 2998d 02h /
34 These updates bring the distribution along to the point where both the GPS
clock subsecond tracking, as well as the OLEDrgb controller now work.		 dgisselq 2998d 04h /
33 Fixed the network receive CRC and MAC checking, and added ip-checking and
minimum packet length checking to the receiver.		 dgisselq 3003d 10h /
32 Brought the CPU to its first working version, to include demo. dgisselq 3004d 13h /
31 Initial network is now working. Adding CPU control files to repository. dgisselq 3005d 06h /
30 Network transmit and MIG memory both work now, though the clock speed has
been dropped to 80.125MHz.		 dgisselq 3005d 06h /
29 Here's the memory pin list, necessary for running Xilinx's Memory Interface
Generator.		 dgisselq 3033d 02h /
28 Including the updates and corrections from the wbuart32 project. dgisselq 3033d 03h /
27 Bus changes ... dgisselq 3033d 03h /
26 Adjusted the timing comments. dgisselq 3033d 03h /
25 The memory now works. However, the core speed has been lowered to 81.25MHz
to do this. The top level file is no longer fasttop.v, but toplevel.v.		 dgisselq 3041d 11h /
24 Here are the updates from the first (failed) attempt to try to integrate
the DDR3 SDRAM controller onto this board.		 dgisselq 3060d 07h /
23 Includes settings necessary for the Arty to load from flash builds, and to
reconfigure itself later.		 dgisselq 3070d 06h /
22 A useful script for programming the device, given that the current device
program includes a valid comms interface.		 dgisselq 3070d 06h /
21 Removed the OLED controller one additional clock from the bus. This was
necessary to maintain the 200MHz clock speed, especially given the growing
fanout of the device bus.		 dgisselq 3070d 06h /

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