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Rev Log message Author Age Path
48 Greatly expanded the specification, including how to's, getting started guide,
register definitions, etc.		 dgisselq 2968d 23h /
47 Updated. dgisselq 2986d 15h /
46 Sped the UART simulator back up to 1MBaud. dgisselq 2986d 15h /
45 Updated the flash, and the flash test bench, for Quad I/O read commands. dgisselq 2986d 15h /
44 Fixed the flash so that it now runs in 1) high speed (41MHz), and 2) that it
doesn't struggle to do read bursts. This should greatly speed up access time.		 dgisselq 2986d 15h /
43 Cleaned up the CPU memory documentation. dgisselq 2986d 15h /
42 Fixed up the CPU so that it passes a multiply test bench, in addition to the
CPU test.		 dgisselq 2986d 15h /
41 Added the CPU test program to the Arty distribution. This works. dgisselq 2986d 15h /
40 Fixed a problem with the declaration of variables to be volatile. dgisselq 2986d 15h /
39 Fixes the OLED test so that it runs using the DMA. dgisselq 2986d 15h /
38 ZipLoad can now load programs to non-reset locations. dgisselq 2986d 15h /
37 Updated documentation and copyright. dgisselq 2986d 15h /
36 Lots of changes, see the git changelog for details. dgisselq 2993d 00h /
35 Added comments and copyright notice. dgisselq 2996d 11h /
34 These updates bring the distribution along to the point where both the GPS
clock subsecond tracking, as well as the OLEDrgb controller now work.		 dgisselq 2996d 13h /
33 Fixed the network receive CRC and MAC checking, and added ip-checking and
minimum packet length checking to the receiver.		 dgisselq 3001d 19h /
32 Brought the CPU to its first working version, to include demo. dgisselq 3002d 22h /
31 Initial network is now working. Adding CPU control files to repository. dgisselq 3003d 15h /
30 Network transmit and MIG memory both work now, though the clock speed has
been dropped to 80.125MHz.		 dgisselq 3003d 15h /
29 Here's the memory pin list, necessary for running Xilinx's Memory Interface
Generator.		 dgisselq 3031d 11h /

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