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Rev	Log message	Author	Age	Path
101	Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source.	olivier.girard	5014d 21h	/
100	Update HTML documentation with Actel's FPGA implementation example (file & directory description section).	olivier.girard	5017d 20h	/
99	Small fix for CVER simulator support.	olivier.girard	5018d 21h	/
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	5018d 21h	/
97	Update Tools' Windows executables with EraseROM command fix.	olivier.girard	5019d 20h	/
96	Fixed EraseROM command in the TCL library of the Software development tools.	olivier.girard	5019d 20h	/
95	Update some test patterns for the additional simulator supports.	olivier.girard	5022d 20h	/
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	5022d 20h	/
93	Update Tools' Windows executables.	olivier.girard	5026d 20h	/
92	Fixed bug where the openmsp430-minidebug application shows data memory size instead of program memory size and program memory size instead of data memory size. Thanks to "dir" for reporting the bug :-)	olivier.girard	5026d 21h	/
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	5026d 21h	/
90	Update windows executables for the tools.	olivier.girard	5042d 03h	/
89	Update the loader tool to support Intel-HEX format.	olivier.girard	5042d 03h	/
88	Update windows executables for the tools.	olivier.girard	5042d 03h	/
87	Minor update of gdbproxy to allow sourcing some custom tcl scripts. Major update of the minidebugger (complete re-work of the GUI).	olivier.girard	5042d 03h	/
86	Update serial debug interface test patterns to make them work with all program memory configurations.	olivier.girard	5049d 18h	/
85	Diverse RTL cosmetic updates.	olivier.girard	5049d 20h	/
84	Update SRAM model in the core testbench to prevent the IEEE warning when running simulations. Update watchdog to fix NMI synchronisation problem. Add synchronizers for the PUC signal in the debug interface.	olivier.girard	5054d 21h	/
83	Add Oscilloscope screenshot + link to the original game.	olivier.girard	5100d 21h	/
82	Update Actel example project: - synthesis scripts. - Spacewar demo program. - SVN ignore patterns for diverse directories	olivier.girard	5100d 21h	/

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Subversion Repositories openmsp430

[/] - Rev 101

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