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Rev	Log message	Author	Age	Path
117	To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license.	olivier.girard	5225d 18h	/
116	Update documentation to reflect the latest core updates.	olivier.girard	5241d 18h	/
115	Add linker script example.	olivier.girard	5250d 18h	/
114	Improved the VerifyCPU_ID procedure.	olivier.girard	5253d 17h	/
113	Created ChangeLog files...	olivier.girard	5254d 17h	/
112	Modified comment.	olivier.girard	5258d 17h	/
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	5259d 17h	/
110	Rework of the GUI for the software development tools. Added possibility to give custom information through the omsp_alias.xml file.	olivier.girard	5260d 17h	/
109	Update Xilinx FPGA example with the latest openMSP430 core RTL version.	olivier.girard	5314d 02h	/
108	Add serial debug interface tasks to the Actel fpga simulation environment.	olivier.girard	5315d 15h	/
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	5315d 15h	/
106	Separated the Timer A defines from the openMSP430 ones. Added the "dbg_en" port in order to allow a separate reset of the debug interface. Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped). Renamed "per_wen" to "per_we" to prevent confusion with active low signals. Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).	olivier.girard	5315d 15h	/
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	5330d 16h	/
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	5334d 17h	/
103	Removed the timescale from all RTL files. Added possibility to exclude the "includes" statements from the RTL.	olivier.girard	5335d 23h	/
102	Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ). The following PUSH instructions are now working as expected: - indexed mode: PUSH x(R1) - indirect register mode: PUSH @R1 - indirect autoincrement: PUSH @R1+	olivier.girard	5336d 15h	/
101	Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source.	olivier.girard	5336d 17h	/
100	Update HTML documentation with Actel's FPGA implementation example (file & directory description section).	olivier.girard	5339d 16h	/
99	Small fix for CVER simulator support.	olivier.girard	5340d 17h	/
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	5340d 17h	/

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[/] - Rev 117

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