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Subversion Repositories openmsp430

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Rev	Log message	Author	Age	Path
121	Add a new FPGA example for the LX9 Microboard from Avnet. Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)	olivier.girard	4877d 18h	/
120	update tools changelog...	olivier.girard	4909d 01h	/
119	Slight improvement of the gdbproxy to improve the support of the EMBSYSREGVIEW Eclipse plugin.	olivier.girard	4909d 02h	/
118	Changelog update (move to modified BSD license).	olivier.girard	4909d 19h	/
117	To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license.	olivier.girard	4909d 19h	/
116	Update documentation to reflect the latest core updates.	olivier.girard	4925d 19h	/
115	Add linker script example.	olivier.girard	4934d 19h	/
114	Improved the VerifyCPU_ID procedure.	olivier.girard	4937d 18h	/
113	Created ChangeLog files...	olivier.girard	4938d 18h	/
112	Modified comment.	olivier.girard	4942d 18h	/
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4943d 18h	/
110	Rework of the GUI for the software development tools. Added possibility to give custom information through the omsp_alias.xml file.	olivier.girard	4944d 18h	/
109	Update Xilinx FPGA example with the latest openMSP430 core RTL version.	olivier.girard	4998d 03h	/
108	Add serial debug interface tasks to the Actel fpga simulation environment.	olivier.girard	4999d 16h	/
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	4999d 16h	/
106	Separated the Timer A defines from the openMSP430 ones. Added the "dbg_en" port in order to allow a separate reset of the debug interface. Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped). Renamed "per_wen" to "per_we" to prevent confusion with active low signals. Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).	olivier.girard	4999d 16h	/
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	5014d 17h	/
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	5018d 18h	/
103	Removed the timescale from all RTL files. Added possibility to exclude the "includes" statements from the RTL.	olivier.girard	5020d 00h	/
102	Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ). The following PUSH instructions are now working as expected: - indexed mode: PUSH x(R1) - indirect register mode: PUSH @R1 - indirect autoincrement: PUSH @R1+	olivier.girard	5020d 16h	/

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