URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] - Rev 121

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
121	Add a new FPGA example for the LX9 Microboard from Avnet. Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)	olivier.girard	4850d 05h	/
120	update tools changelog...	olivier.girard	4881d 12h	/
119	Slight improvement of the gdbproxy to improve the support of the EMBSYSREGVIEW Eclipse plugin.	olivier.girard	4881d 13h	/
118	Changelog update (move to modified BSD license).	olivier.girard	4882d 06h	/
117	To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license.	olivier.girard	4882d 06h	/
116	Update documentation to reflect the latest core updates.	olivier.girard	4898d 06h	/
115	Add linker script example.	olivier.girard	4907d 06h	/
114	Improved the VerifyCPU_ID procedure.	olivier.girard	4910d 05h	/
113	Created ChangeLog files...	olivier.girard	4911d 06h	/
112	Modified comment.	olivier.girard	4915d 05h	/
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4916d 05h	/
110	Rework of the GUI for the software development tools. Added possibility to give custom information through the omsp_alias.xml file.	olivier.girard	4917d 05h	/
109	Update Xilinx FPGA example with the latest openMSP430 core RTL version.	olivier.girard	4970d 14h	/
108	Add serial debug interface tasks to the Actel fpga simulation environment.	olivier.girard	4972d 03h	/
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	4972d 03h	/
106	Separated the Timer A defines from the openMSP430 ones. Added the "dbg_en" port in order to allow a separate reset of the debug interface. Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped). Renamed "per_wen" to "per_we" to prevent confusion with active low signals. Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).	olivier.girard	4972d 04h	/
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	4987d 04h	/
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4991d 06h	/
103	Removed the timescale from all RTL files. Added possibility to exclude the "includes" statements from the RTL.	olivier.girard	4992d 11h	/
102	Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ). The following PUSH instructions are now working as expected: - indexed mode: PUSH x(R1) - indirect register mode: PUSH @R1 - indirect autoincrement: PUSH @R1+	olivier.girard	4993d 04h	/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories openmsp430

[/] - Rev 121

Filtering Options